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1 S3038 sonet/sdh/atm oc-12 quad transceiver may 31, 2001 / revision c bicmos lvpecl clock generator ? device specification sonet/sdh/atm oc-12 transmitter and receiver S3038 features ? complies with bellcore and itu-t specifications ? supports 622.08 mbps (oc-12) ? quad transmitter incorporating phase-lock loop (pll) clock synthesis from a low-speed reference clock ? quad receiver pll provides clock and data recovery ? selectable reference frequencies of 38.88 mhz, or 77.76 mhz ? interface to both lvpecl and ttl logic ? 8-bit ttl datapath ? compact 23mm x 23mm 208 tbga package ? diagnostic loopback mode ? low jitter lvpecl interface ? single 3.3v supply ? local loopback applications ? sonet/sdh-based transmission systems ? sonet/sdh modules ? sonet/sdh test equipment ? atm over sonet/sdh ? section repeaters ? add drop multiplexers (adm) ? broad-band cross-connects ? fiber optic terminators ? fiber optic test equipment sonet/sdh/atm oc-12 quad transceiver S3038 general description the S3038 sonet/sdh quad transceiver chip is a fully integrated serialization/deserialization sonet oc-12 (622.08 mbit/s) interface device. the chip performs all necessary serial-to-parallel and parallel- to-serial functions in conformance with sonet/sdh transmission standards. the device is suitable for sonet-based atm applications. figure 1 shows a typical network application. on-chip clock synthesis is performed by the high- frequency phase-lock loop on the S3038 quad transceiver chip allowing the use of a slower external transmit clock reference. clock recovery is performed on the device by synchronizing its on-chip vco di rectly to the incoming data stream. the S3038 also per- forms sonet/sdh frame detection. the chip can be used with a 38.88 mhz, or 77.76 mhz reference clock, in support of existing system clocking schemes. the low jitter lvpecl interface guarantees compli ance with the bit-error rate requirements of the bellcore and itu-t standards. the S3038 is packaged in a 23mm x 23mm 208 tbga.
2 S3038 sonet/sdh/atm oc-12 quad transceiver may 31, 2001 / revision c figure 1. system block diagram network interface processor network interface processor 8 8 8 8 sonet/sdh transceiver a sonet/sdh transceiver a otx orx otx orx 2 2 2 otx orx 2 2 2 otx orx 2 2 8 8 8 8 sonet/sdh transceiver b sonet/sdh transceiver b otx orx otx orx 2 2 2 otx orx 2 2 2 otx orx 2 2 8 8 8 8 sonet/sdh transceiver c sonet/sdh transceiver c otx orx otx orx 2 2 2 otx orx 2 2 2 otx orx 2 2 8 8 8 8 sonet/sdh transceiver d sonet/sdh transceiver d otx orx otx orx 2 2 2 otx orx 2 2 2 otx orx 2 2 S3038 S3038
3 S3038 sonet/sdh/atm oc-12 quad transceiver may 31, 2001 / revision c figure 2. S3038 input/output diagram 8 8 8 8 8 8 8 8 refclk reset pclk pina[7:0] pinb[7:0] pinc[7:0] pind[7:0] piclka piclkb piclkc piclkd poclkap/n fpa poclkbp/n fpb poclkcp/n fpc poclkdp/n fpd pouta[7:0] poutb[7:0] poutc[7:0] poutd[7:0] ch_lock oof clksel tmode tsda0p/n tsda1p/n tsdb0p/n tsdb1p/n tsdc0p/n tsdc1p/n tsdd0p/n tsdd1p/n rsda0p/n rsda1p/n rsdb0p/n rsdb1p/n rsdc0p/n rsdc1p/n rsdd0p/n rsdd1p/n rsdasel rsdbsel rsdcsel rsddsel dleb sdttl S3038 cap1 cap2
4 S3038 sonet/sdh/atm oc-12 quad transceiver may 31, 2001 / revision c figure 3. transmitter block diagram 8 pina[7:0] tsda1p tsda1n tsda0p tsda0n tsdabp 8 shift reg 8 pinb[7:0] tsdb1p tsdb1n tsdb0p tsdb0n tsdbbp 8 shift reg piclkb 8 pinc[7:0] tsdc1p tsdc1n tsdc0p tsdc0n tsdcbp 8 shift reg piclkc 8 pind[7:0] tsdd1p tsdd1n tsdd0p tsdd0n tsddbp 8 shift reg piclkd tx pll 8x/16x refclk clksel mux refclk pclk fifo (input) fifo (input) fifo (input) fifo (input) piclka 0 1 2 3 ch_lock 0 1 2 3 0 1 2 3 0 1 2 3 ch_lock piclkb piclkc tmode
5 S3038 sonet/sdh/atm oc-12 quad transceiver may 31, 2001 / revision c figure 4. receiver block diagram rx cru serial- parallel rx cru serial- parallel pouta[7:0] rsda0p rsda0n rsda1p rsda1n rsdasel sdttla oofa rsdb0p rsdb0n rsdb1p rsdb1n rsdbsel sdttlb oofb poutb[7:0] q fifo (output) rx cru serial- parallel poutd[7:0] rsdd0p rsdd0n rsdd1p rsdd1n rsddsel dleb sdttld oofd rx cru serial- parallel poutc[7:0] rsdc0p rsdc0n rsdc1p rsdc1n rsdcsel sdttlc oofc tsddbp tsdcbp tsdbbp tsdabp refclk 8 8 8 8 poclkap/n poclkbp/n poclkcp/n poclkdp/n fifo (output) fifo (output) fifo (output) ch_lock receiver core a receiver core b receiver core c receiver core d framing data stretching timing framing data stretching timing framing data stretching timing framing data stretching timing fpd fpc fpb fpa
6 S3038 sonet/sdh/atm oc-12 quad transceiver may 31, 2001 / revision c sonet overview synchronous optical network (sonet) is a stan- dard for connecting one fiber system to another at the optical level. sonet, together with the synchro- nous digital hierarchy (sdh) administered by the itu-t, forms a single international standard for fiber interconnect between telephone networks of differ- ent countries. sonet is capable of accommodating a variety of transmission rates and applications. the sonet standard is a layered protocol with four separate layers defined. these are: ? photonic ? section ? line ? path figure 5 shows the layers and their functions. each of the layers has overhead bandwidth dedicated to administration and maintenance. the photonic layer simply handles the conversion from electrical to opti- cal and back with no overhead. it is responsible for transmitting the electrical signals in optical form over the physical media. the section layer handles the transport of the framed electrical signals across the optical cable from one end to the next. key functions of this layer are framing, scrambling, and error moni- toring. the line layer is responsible for the reliable transmission of the path layer information stream carrying voice, data, and video signals. its main functions are synchronization, multiplexing, and reli- able transport. the path layer is responsible for the actual transport of services at the appropriate signal- ing rates. data rates and signal hierarchy table 1 contains the data rates and signal designa tions of the sonet hierarchy. the lowest level is the basic sonet signal referred to as the synchronous trans port signal level-1 (sts-1). an sts- n signal is made up of n byte-interleaved sts-1 signals. the optical counterpart of each sts- n signal is an optical carrier level- n signal (oc- n ). the S3038 chip supports oc- 12 rates (622.08 mbps). frame and byte boundary detection the sonet/sdh fundamental frame format for sts-12 consists of 36 transport overhead bytes fol- lowed by synchronous payload envelope (spe) bytes. this pattern of 36 overhead and 1044 spe bytes is repeated nine times in each frame. frame and byte boundaries are detected using the a1 and a2 bytes found in the transport overhead. (see figure 6.) for more details on sonet operations, refer to the bellcore sonet standard document. table 1. sonet signal hierarchy figure 5. sonet structure figure 6. stsC12/ocC12 frame format 9 rows 12 a1 bytes 12 a2 bytes a1 a1 a1 a1 a2 a2 a2 a2 transport overhead 36 columns 36 x 9 = 324 bytes synchronous payload envelope 1044 columns 1044 x 9 = 9396 bytes 125 sec s s . c e l et t i c cl a c i t p o) s p b m ( e t a r a t a d 1 - s t s1 - c o4 8 . 1 5 3 - s t s1 - m t s3 - c o2 5 . 5 5 1 2 1 - s t s 4 - m t s 2 1 - c o 8 0 . 2 2 6 4 2 - s t s8 - m t s4 2 - c o6 1 . 4 4 2 1 8 4 - s t s6 1 - m t s8 4 - c o2 3 . 8 8 4 2 0 bps end equipment end equipment payload to spe mapping maintenance, protection, switching optical transmission scrambling, framing fiber cable section layer line layer path layer photonic layer section layer line layer path layer photonic layer layer overhead (embedded ops channel) functions 576 kbps 192 kbps
7 S3038 sonet/sdh/atm oc-12 quad transceiver may 31, 2001 / revision c S3038 overview the S3038 quad transceiver implements sonet/ sdh serialization/deserialization, transmission, and frame detection/recovery functions. this chip can be used to implement the front end of sonet equip- ment, which consists primarily of the serial transmit interface and the serial receive interface. the chip handles all the functions of these two ele ments, in- cluding parallel-to-serial and serial-to-parallel conversion, clock generation and recovery, and sys- tem timing. the system timing circuitry consists of management of the datastream, framing, and clock distribution throughout the front end. the S3038 is divided into a transmitter section and a receiver section. the sequence of operations is as follows: transmitter operations: 1. 8-bit parallel input 2. parallel-to-serial conversion 3. serial output receiver operations: 1. clock and data recovery from serial input 2. frame detection 3. serial-to-parallel conversion 4. 8-bit parallel output internal clocking and control functions are transpar- ent to the user.
8 S3038 sonet/sdh/atm oc-12 quad transceiver may 31, 2001 / revision c functional description quad transmitter operation the S3038 quad transceiver chip performs the seri- alizing stage in the processing of a transmit sonet sts-12 bit serial data stream. it converts the 8-bit parallel 77.76 mbyte/sec data stream into a bit serial format at 622.08 mbps. a high-frequency bit clock can be generated from a 77.76 mhz frequency reference by using an integral frequency synthesizer consisting of a phase-lock loop circuit with a divider in the loop. diagnostic loopback is provided (transmitter to re- ceiver). see other operating modes. clock synthesizer the clock synthesizer is a monolithic pll that gener- ates the serial output clock phase synchronized with the input reference clock (refclk). the refclk input must be generated from a crys- tal oscillator which has a frequency accuracy that meets the value stated in table 11. the on-chip pll consists of a phase detector, which compares the phase relationship between the vco output and the refclk input, a loop filter which converts the phase detector output into a smooth dc voltage, and a vco, whose frequency is varied by this voltage. the loop filter generates a vco control voltage based on the average dc level of the phase discrimi- nator output pulses. a single external clean-up capacitor is utilized as part of the loop filter. the loop filters corner frequency is optimized to minimize out- put phase jitter. timing generator the timing generation function provides an 8-bit par- allel rate version of the transmit serial clock. this circuitry also provides an internally gen erated load sig- nal, which transfers the pin[7:0] data from the parallel input register to the serial shift register. the pclk output is an 8-bit parallel rate version of the transmit serial clock at 77.76 mhz. pclk is in- tended for use as an 8-bit parallel clock for upstream multiplexing and overhead processing circuits. using pclk for upstream circuits will ensure a stable fre- quency and phase relationship between the data coming into and leaving the S3038 device. parallel-to-serial converter the parallel-to-serial converter is comprised of two 8-bit parallel registers. the first register latches the data from the pin[7:0] bus on the rising edge of piclk. the second register is a parallel loadable shift register which takes its parallel input from the first register. the load signal, which latches the data from the par- allel to the serial shift register, has a fixed relationship to pclk. if piclk is tied to pclk, the pin[7:0] data latched into the parallel register will meet the timing specifications with respect to the load signal. if piclk is not tied to pclk, the delay must meet the timing requirements. redundant outputs two high-speed differential outputs are provided for each channel. this enables each channel to drive a primary and secondary switch fabric for sonet ap- plications in which redundancy is required to achieve higher reliability. routing of signals for channel-lock operation when operating in the channel lock (ch_lock) mode, the user must ensure that the path length of the four high-speed serial data signals are matched to within 3 ns of delay. failure to meet this require- ment may result in bit errors in the received data or in byte misalignment. table 2. reference frequency options table 3. reference jitter limits r e t t i j k c o l c e c n e r e f e r m u m i x a m d n a b z h m 5 o t z h k 2 1 n i g n i t a r e p o e d o m s m r s p 4 12 1 C s t s l e s k l c k c o l c e c n e r e f e r y c n e u q e r f g n i t a r e p o e d o m 1z h m 8 8 . 8 32 1 - s t s 0z h m 6 7 . 7 72 1 - s t s
9 S3038 sonet/sdh/atm oc-12 quad transceiver may 31, 2001 / revision c figure 7. pin data clocking with piclk figure 8. refclk forward pin clocking refclk S3038 piclkx pinx[7:0] ref oscillator mac asic pclk pll refclk S3038 piclkx pinx[7:0] ref oscillator mac asic pclk pll the following figures illustrate the broad range of transmit data clocking options supported by the S3038. figure 7 demonstrates the flexibility afforded by the S3038. a low jitter reference is provided directly to the S3038 at either 1/8 or 1/16 the serial data rate. this ensures minimum jitter in the synthesized clock used for serial data transmission. a system clock output at the 32-bit parallel rate, pclk, is derived from the pll and provided to the upstream circuit as a system clock. this clock can be buffered as re- quired without concern about added delay. there is no phase requirement placed upon pclk and the piclkx clock, which is provided back to the S3038, other than that they remain within 3 ns of the phase relationship established at reset. the S3038 also supports the traditional refclk clocking and is illustrated in figure 8. this approach imposes significant challenges in maintaining timing margins on the designer.
10 S3038 sonet/sdh/atm oc-12 quad transceiver may 31, 2001 / revision c the phase relationship between the edge transitions of the data and those of the generated clock are compared by a phase/frequency discriminator. out- put pulses from the discriminator indicate the required direction of phase corrections. these pulses are smoothed by an integral loop filter. the output of the loop filter controls the frequency of the voltage controlled oscillator (vco), which gener- ates the recovered clock. frequency stability without incoming data is guaran- teed by an alternate reference input (refclk) that the pll locks onto when data is lost. if the frequency of the incoming signal varies by greater than the value stated in table 11 with respect to refclk, the pll will be declared out of lock, and the pll will lock to the reference clock. the assertion of los will also cause an out of lock condition. the loop filter transfer function is optimized to en- able the pll to track the jitter, yet tolerate the minimum transition density expected in a received sonet data signal. the total loop dynamics of the clock recovery pll yield a jitter tolerance which exceeds the minimum tolerance proposed for sonet equipment by the bellcore ta-nwt-000253 standard, shown in figure 9. figure 9. clock recovery jitter tolerance 25k 65k 250k 5m 6.5k 300 30 0.15 1.5 15 jitter frequency (hz) jitter amplitude (ul p-p) minimum proposed tolerance (ta-nwt-000253) oc-12 clock recovery clock recovery generates a clock that is at the same frequency as the incoming data bit rate at the rsd input or, in loopback, the transmitter data output. the clock is phase aligned by a phase locked loop (pll) so that it samples the data in the center of the data eye pattern. receiver operation the S3038 quad transceiver chip provides the first stage of digital processing of a receive sonet sts- 12 bit-serial stream. it converts the bit-serial 622.08 mbps data stream into a 77.76 mbyte/sec 8-bit paral- lel data format. data input two differential receivers are provided for each channel of the S3038. this supports switching be- tween redundant switch fabrics for sonet applications. a select signal rsdsel is provided for each channel to control the selection of primary or secondary inputs. in addition, each channel supports a diagnostic loopback mode in which the serial data from the transmitter replaces external serial data. the loopback functions for all four channels is con- trolled by a single diagnostic loopback enable (dleb) signal. clock recovery is performed on the incoming scrambled nrz data stream. a 77.76 mhz reference clock is required for phase locked loop start-up and proper operation under loss of signal conditions. an integral prescaler and phase locked loop circuit is used to multiply this reference to the nominal bit rate. a loopback mode is provided for diagnostic loopback (transmitter to receiver).
11 S3038 sonet/sdh/atm oc-12 quad transceiver may 31, 2001 / revision c frame and byte boundary detection the frame and byte boundary detection circuitry searches the incoming data for three consecutive a1 bytes followed immediately by three consecutive a2 bytes. framing pattern detection is enabled and dis- abled by the out-of-frame (oof) input. detection is enabled by a rising edge on oof, and remains en- abled for the duration that oof is set high. it is disabled when a framing pattern is detected and oof is no longer set high. when the framing pattern detection is enabled, the framing pattern is used to locate byte and frame boundaries in the incoming data stream (rsd or looped transmitter data). the timing generator block takes the located byte bound- ary and uses it to block the incoming data stream into bytes for output on the parallel output data bus (pout[7:0]). the frame boundary is reported on the frame pulse (fp) output when any 48-bit pattern matching the framing pattern is detected on the in- coming data stream. when the framing pattern detection is disabled, the byte boundary is frozen to the location found when detection was previously enabled. only framing patterns aligned to the fixed byte boundary are indicated on the fp output. the probability that random data in an sts-12 stream will generate the 48-bit framing pattern is extremely small. it is highly improbable that a mimic pattern would occur within one frame of data. therefore, the time to match the first frame pattern and to verify it with down-stream circuitry, at the next occurrence of the pattern, is expected to be less than the required 250 m s, even for extremely high bit error rates. once down-stream overhead circuitry has verified that frame and byte synchronization are correct, the oof input can be set low to disable the frame search process from trying to synchronize to a mimic frame pattern serial-to-parallel converter the serial-to-parallel converter consists of three 8-bit registers. the first is a serial-in, parallel-out shift reg- ister, which performs serial to parallel conversion clocked by the clock recovery block. the second is an 8-bit internal holding register, which transfers data from the serial to parallel register on byte boundaries as determined by the frame and byte boundary detection block. on the falling edge of the free running poclk, the data in the holding register is transferred to an output holding register which drives pout[7:0]. the delay through the serial-to-parallel converter can vary from 1.5 to 3.5 byte periods (12 to 28 serial bit periods) measured from the first bit of an incom- ing byte to the beginning of the parallel output of that byte. the variation in the delay is dependent on the alignment of the internal parallel load timing, which is synchronized to the data byte boundaries, with re spect to the falling edge of poclk, which is independent of the byte boundaries. the advantage of this serial to parallel converter is that poclk is nei- ther truncated nor extended during reframe sequences. other operating modes diagnostic loopback when the diagnostic loopback enable (dleb) input is active, a loopback from the transmitter to the re- ceiver at the serial data rate can be set up for diagnostic purposes. the differential serial output data from the transmitter is routed to the serial-to- parallel block in place of the normal data stream (rsd). forward clocking for 77.76 mhz reference operation, the S3038 oper- ates in the forward clocking mode. the pll locks the pclk output of the transmitter section to the refclk with a fixed and repeatable phase relation. this allows the transmitter data source to also be the timing source for the serial clock synthesis. the rising edge of pclk is locked to the rising edge of refclk, with a maximum delay of 8 to 10 nsec due to the pclk ttl output driver. reset the reset signal initializes the internal counters, in addition, the rising edge on oof is required after reset to initialize the chip.
12 S3038 sonet/sdh/atm oc-12 quad transceiver may 31, 2001 / revision c table 4. transmitter input signals pin assignment and descriptions e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d 0 a n i p 1 a n i p 2 a n i p 3 a n i p 4 a n i p 5 a n i p 6 a n i p 7 a n i p l t ti 2 1 p 2 1 r 3 1 t 2 1 t 3 1 u 1 1 p 1 1 r 1 1 t d e k c o l c s i s u b s i h t n o a t a d l e l l a r a p . a l e n n a h c r o f a t a d t i m s n a r t . k l c f e r r o a k l c i p f o e g d e g n i s i r e h t n o n i a k l c i pl t ti 2 1 un o a t a d k c o l c o t d e s u s i l a n g i s s i h t . a k c o l c a t a d t i m s n a r t n o a t a d k c o l c o t d e s u e b o s l a n a c l a n g i s s i h t . ] 0 : 7 [ a n i p . ] 0 : 7 [ d n i p d n a ] 0 : 7 [ c n i p , ] 0 : 7 [ b n i p 0 b n i p 1 b n i p 2 b n i p 3 b n i p 4 b n i p 5 b n i p 6 b n i p 7 b n i p l t ti 5 1 r 4 1 p 5 1 t 4 1 r 7 1 u 6 1 u 3 1 p 4 1 t d e k c o l c s i s u b s i h t n o a t a d l e l l a r a p . b l e n n a h c r o f a t a d t i m s n a r t . k l c f e r r o b k l c i p , a k l c i p f o e g d e g n i s i r e h t n o n i b k l c i pl t ti 3 1 rn o a t a d k c o l c o t d e s u s i l a n g i s s i h t . b k c o l c a t a d t i m s n a r t . ] 0 : 7 [ b n i p 0 c n i p 1 c n i p 2 c n i p 3 c n i p 4 c n i p 5 c n i p 6 c n i p 7 c n i p l t ti 5 1 m 6 1 n 4 1 m 7 1 r 6 1 p 5 1 n 7 1 t 4 1 n d e k c o l c s i s u b s i h t n o a t a d l e l l a r a p . c l e n n a h c r o f a t a d t i m s n a r t . k l c f e r r o c k l c i p , a k l c i p f o e g d e g n i s i r e h t n o n i c k l c i pl t ti 5 1 pn o a t a d k c o l c o t d e s u s i l a n g i s s i h t . c k c o l c a t a d t i m s n a r t . ] 0 : 7 [ c n i p 0 d n i p 1 d n i p 2 d n i p 3 d n i p 4 d n i p 5 d n i p 6 d n i p 7 d n i p l t ti 7 1 l 6 1 k 5 1 k 4 1 k 7 1 m 6 1 l 6 1 m 5 1 l d e k c o l c s i s u b s i h t n o a t a d l e l l a r a p . d l e n n a h c r o f a t a d t i m s n a r t . k l c f e r r o , d k l c i p , a k l c i p f o e g d e g n i s i r e h t n o n i d k l c i pl t ti 4 1 ln o a t a d k c o l c o t d e s u s i l a n g i s s i h t . d k c o l c a t a d t i m s n a r t . ] 0 : 7 [ d n i p
13 S3038 sonet/sdh/atm oc-12 quad transceiver may 31, 2001 / revision c table 6. transmitter control signals pin assignment and descriptions e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d k c o l _ h cl t ti4 en e h w . h g i h e v i t c a . l o r t n o c e d o m t u p n i l e l l a r a p . k c o l l e n n a h c . r e h t e g o t s l e n n a h c r u o f l l a s k c o l l a n g i s s i h t , e v i t c a e d o m tl t ti 3 1 bd e s u s i k l c f e r , w o l s i e d o m t n e h w . l o r t n o c e d o m t i m s n a r t d e s u s i x k l c i p , h g i h s i e d o m t n e h w . ] 0 : 7 [ x n i p n o a t a d k c o l c o t r u o f l l a , e d o m k c o l l e n n a h c n i . 8 3 0 3 s e h t o t n i a t a d k c o l c o t - n a h c ( e d o m t n e d n e p e d n i n i . a k l c i p y b d e k c o l c e r a s l e n n a h c . k l c i p e v i t c e p s e r s t i y b d e k c o l c s i l e n n a h c h c a e ) w o l k c o l l e s k l cl t ti 2 1 ce h t r o f l l p e h t s e r u g i f n o c l a n g i s s i h t . t u p n i t c e l e s k l c f e r k l c f e r e h t , 0 = l e s k l c n e h w . y c n e u q e r f k l c f e r e t a i r p o r p p a = l e s k l c n e h w . e t a r l e l l a r a p t i b - 2 3 e h t l a u q e d l u o h s y c n e u q e r f . e t a r a t a d l e l l a r a p e h t 2 / 1 e b d l u o h s y c n e u q e r f k l c f e r e h t , 1 k l c f e rl t ti 7 1 hy c n e u q e r f a s a d n a o c v t i m s n a r t e h t r o f d e s u k c o l c e c n e r e f e r . a t a d l a i r e s r e v i e c e r e h t m o r f d e r e v o c e r k c o l c e h t r o f k c e h c r u o f l l a f o a t a d t u p n i e h t k c o l c o t d e s u e b o s l a n a c k l c f e r . s l e n n a h c t e s e rl t ti 5 1 cd e c r o f s i l l p r e v i e c e r e h t . t e s e r n i d l e h s i 8 3 0 3 s e h t , w o l n e h w g n i s i r e h t n o d e z i l a i t i n i e r a s ' o f i f e h t . k l c f e r e h t o t k c o l o t . y l l a m r o n s e t a r e p o 8 3 0 3 s e h t , h g i h n e h w . t e s e r f o e g d e e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d p 0 a d s t n 0 a d s t . f f i d l c e p v l o7 1 a 7 1 b . a l e n n a h c r o f s t u p t u o l a i r e s d e e p s h g i h y r a m i r p p 1 a d s t n 1 a d s t . f f i d l c e p v l o4 1 e 6 1 d . a l e n n a h c r o f s t u p t u o l a i r e s d e e p s h g i h y r a d n o c e s p 0 b d s t n 0 b d s t . f f i d l c e p v l o7 1 c 7 1 d . b l e n n a h c r o f s t u p t u o l a i r e s d e e p s h g i h y r a m i r p p 1 b d s t n 1 b d s t . f f i d l c e p v l o4 1 f 5 1 f . b l e n n a h c r o f s t u p t u o l a i r e s d e e p s h g i h y r a d n o c e s p 0 c d s t n 0 c d s t . f f i d l c e p v l o6 1 f 7 1 e . c l e n n a h c r o f s t u p t u o l a i r e s d e e p s h g i h y r a m i r p p 1 c d s t n 1 c d s t . f f i d l c e p v l o5 1 g 4 1 g . c l e n n a h c r o f s t u p t u o l a i r e s d e e p s h g i h y r a d n o c e s p 0 d d s t n 0 d d s t . f f i d l c e p v l o7 1 f 7 1 g . d l e n n a h c r o f s t u p t u o l a i r e s d e e p s h g i h y r a m i r p p 1 d d s t n 1 d d s t . f f i d l c e p v l o4 1 h 5 1 h . d l e n n a h c r o f s t u p t u o l a i r e s d e e p s h g i h y r a d n o c e s k l c pl t to 4 1 jd e d i v o r p s i k c o l c s i h t . e t a r a t a d l e l l a r a p e h t t a k c o l c t u p t u o l t t . y r t i u c r i c m a e r t s - p u e h t y b e s u r o f table 5. transmitter output signals pin assignment and descriptions note: all inputs have internal pull-up networks.
14 S3038 sonet/sdh/atm oc-12 quad transceiver may 31, 2001 / revision c table 7. receiver output signals pin assignment and descriptions e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d 0 a t u o p 1 a t u o p 2 a t u o p 3 a t u o p 4 a t u o p 5 a t u o p 6 a t u o p 7 a t u o p l t to1 j 3 j 2 j 1 h 2 h 3 h 1 f 2 g s i s u b s i h t n o a t a d l e l l a r a p . s t u p t u o a t a d r e v i e c e r a l e n n a h c . p a k l c o p f o e g d e g n i s i r e h t n o d i l a v a p fl t to2 fs a h a t a d d i l a v t a h t s e t a c i d n i t u p t u o s i h t n o h g i h a . e s l u p e m a r f t u p t u o a t a d l e l l a r a p e h t n o t n e s e r p s i d n a d e t c e t e d n e e b . ] 0 : 7 [ a t u o p p a k l c o p n a k l c o p l t to2 k 1 k d i l a v e r a , ] 0 : 7 [ a t u o p , a t a d e v i e c e r l e l l a r a p . k c o l c a t a d e v i e c e r . p a k l c o p f o e g d e g n i s i r e h t n o 0 b t u o p 1 b t u o p 2 b t u o p 3 b t u o p 4 b t u o p 5 b t u o p 6 b t u o p 7 b t u o p l t to1 r 1 p 3 m 2 n 2 m 1 n 2 l 1 m s i s u b s i h t n o a t a d l e l l a r a p . s t u p t u o a t a d r e v i e c e r b l e n n a h c . p b k l c o p f o e g d e g n i s i r e h t n o d i l a v b p fl t to1 ls a h a t a d d i l a v t a h t s e t a c i d n i t u p t u o s i h t n o h g i h a . e s l u p e m a r f t u p t u o a t a d l e l l a r a p e h t n o t n e s e r p s i d n a d e t c e t e d n e e b . ] 0 : 7 [ b t u o p p b k l c o p n b k l c o p l t to1 u 1 t d i l a v e r a ] 0 : 7 [ b t u o p , a t a d e v i e c e r l e l l a r a p . k c o l c a t a d e v i e c e r . p b k l c o p f o e g d e g n i s i r e h t n o 0 c t u o p 1 c t u o p 2 c t u o p 3 c t u o p 4 c t u o p 5 c t u o p 6 c t u o p 7 c t u o p l t to7 r 6 r 5 t 3 u 4 t 5 r 2 u 3 t s i s u b s i h t n o a t a d l e l l a r a p . s t u p t u o a t a d r e v i e c e r c l e n n a h c . p c k l c o p f o e g d e g n i s i r e h t n o d i l a v c p fl t to2 rs a h a t a d d i l a v t a h t s e t a c i d n i t u p t u o s i h t n o h g i h a . e s l u p e m a r f t u p t u o a t a d l e l l a r a p e h t n o t n e s e r p s i d n a d e t c e t e d n e e b . ] 0 : 7 [ c t u o p p c k l c o p n c k l c o p l t to5 u 4 u d i l a v e r a ] 0 : 7 [ c t u o p , a t a d e v i e c e r l e l l a r a p . k c o l c a t a d e v i e c e r . p c k l c o p f o e g d e g n i s i r e h t n o
15 S3038 sonet/sdh/atm oc-12 quad transceiver may 31, 2001 / revision c table 7. receiver output signals pin assignment and descriptions (continued) e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d 0 d t u o p 1 d t u o p 2 d t u o p 3 d t u o p 4 d t u o p 5 d t u o p 6 d t u o p 7 d t u o p l t to 1 1 u 0 1 r 9 u 9 r 9 t 8 u 7 u 8 t s i s u b s i h t n o a t a d l e l l a r a p . s t u p t u o a t a d r e v i e c e r d l e n n a h c . p d k l c o p f o e g d e g n i s i r e h t n o d i l a v d p fl t to6 us a h a t a d d i l a v t a h t s e t a c i d n i t u p t u o s i h t n o h g i h a . e s l u p e m a r f t u p t u o a t a d l e l l a r a p e h t n o t n e s e r p s i d n a d e t c e t e d n e e b . ] 0 : 7 [ d t u o p p d k l c o p n d k l c o p l t to 0 1 t 0 1 u d i l a v e r a ] 0 : 7 [ d t u o p , a t a d e v i e c e r l e l l a r a p . k c o l c a t a d e v i e c e r . p d k l c o p f o e g d e g n i s i r e h t n o
16 S3038 sonet/sdh/atm oc-12 quad transceiver may 31, 2001 / revision c table 8. receiver input signals pin assignment and description e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d p 0 a d s r n 0 a d s r . f f i d l c e p v l i5 d 5 c . a l e n n a h c r o f s t u p n i e l b i t a p m o c l c e p v l l a i t n e r e f f i d y r a m i r p y l l a n r e t n i . e v i t a g e n e h t s i n 0 a d s r , t u p n i e v i t i s o p e h t s i p 0 a d s r . s n o i t a c i l p p a d e l p u o c c a r o f v 3 . 1 - d d v o t d e s a i b p 1 a d s r n 1 a d s r . f f i d l c e p v l i4 d 3 b . a l e n n a h c r o f s t u p n i e l b i t a p m o c l c e p v l l a i t n e r e f f i d y r a d n o c e s y l l a n r e t n i . e v i t a g e n e h t s i n 1 a d s r , t u p n i e v i t i s o p e h t s i p 1 a d s r . s n o i t a c i l p p a d e l p u o c c a r o f v 3 . 1 - d d v o t d e s a i b l e s a d s rl t ti3 ah g i h , 0 a d s r t u p n i s t c e l e s w o l . l o r t n o c t c e l e s t u p n i a l e n n a h c ) . d e t c e n n o c t o n n e h w p u - l l u p l a n r e t n i ( . 1 a d s r s t c e l e s p 0 b d s r n 0 b d s r . f f i d l c e p v l i6 c 5 b . b l e n n a h c r o f s t u p n i e l b i t a p m o c l c e p v l l a i t n e r e f f i d y r a m i r p y l l a n r e t n i . e v i t a g e n e h t s i n 0 b d s r , t u p n i e v i t i s o p e h t s i p 0 b d s r . s n o i t a c i l p p a d e l p u o c c a r o f v 3 . 1 - d d v o t d e s a i b p 1 b d s r n 1 b d s r . f f i d l c e p v l i7 c 7 d . b l e n n a h c r o f s t u p n i e l b i t a p m o c l c e p v l l a i t n e r e f f i d y r a d n o c e s y l l a n r e t n i . e v i t a g e n e h t s i n 1 b d s r , t u p n i e v i t i s o p e h t s i p 1 b d s r . s n o i t a c i l p p a d e l p u o c c a r o f v 3 . 1 - d d v o t d e s a i b l e s b d s rl t ti5 ah g i h , 0 b d s r t u p n i s t c e l e s w o l . l o r t n o c t c e l e s t u p n i b l e n n a h c ) . d e t c e n n o c t o n n e h w p u - l l u p l a n r e t n i ( . 1 b d s r s t c e l e s p 0 c d s r n 0 c d s r . f f i d l c e p v l i0 1 a 9 b . c l e n n a h c r o f s t u p n i e l b i t a p m o c l c e p v l l a i t n e r e f f i d y r a m i r p y l l a n r e t n i . e v i t a g e n e h t s i d s r , t u p n i e v i t i s o p e h t s i p 0 c d s r . s n o i t a c i l p p a d e l p u o c c a r o f v 3 . 1 - d d v o t d e s a i b p 1 c d s r n 1 c d s r . f f i d l c e p v l i8 a 9 a . c l e n n a h c r o f s t u p n i e l b i t a p m o c l c e p v l l a i t n e r e f f i d y r a d n o c e s y l l a n r e t n i . e v i t a g e n e h t s i n 1 c d s r , t u p n i e v i t i s o p e h t s i p 1 c d s r . s n o i t a c i l p p a d e l p u o c c a r o f v 3 . 1 - d d v o t d e s a i b l e s c d s rl t ti9 ch g i h , 0 c d s r t u p n i s t c e l e s w o l . l o r t n o c t c e l e s t u p n i c l e n n a h c ) . d e t c e n n o c t o n n e h w p u - l l u p l a n r e t n i ( . 1 c d s r s t c e l e s p 0 d d s r n 0 d d s r . f f i d l c e p v l i0 1 c 0 1 d . d l e n n a h c r o f s t u p n i e l b i t a p m o c l c e p v l l a i t n e r e f f i d y r a m i r p y l l a n r e t n i . e v i t a g e n e h t s i n 0 d d s r , t u p n i e v i t i s o p e h t s i p 0 d d s r . s n o i t a c i l p p a d e l p u o c c a r o f v 3 . 1 - d d v o t d e s a i b p 1 d d s r n 1 d d s r . f f i d l c e p v l i1 1 c 2 1 b . d l e n n a h c r o f s t u p n i e l b i t a p m o c l c e p v l l a i t n e r e f f i d y r a d n o c e s y l l a n r e t n i . e v i t a g e n e h t s i n 1 d d s r , t u p n i e v i t i s o p e h t s i p 1 d d s r . s n o i t a c i l p p a d e l p u o c c a r o f v 3 . 1 - d d v o t d e s a i b l e s d d s rl t ti 1 1 bh g i h , 0 d d s r t u p n i s t c e l e s w o l . l o r t n o c t c e l e s t u p n i d l e n n a h c ) . d e t c e n n o c t o n n e h w p u - l l u p l a n r e t n i ( . 1 d d s r s t c e l e s a f o o b f o o c f o o d f o o l t t v li4 1 u 6 1 t 7 1 p 7 1 k n o i t c e t e d n r e t t a p g n i m a r f e l b a n e o t d e s u r o t a c i d n i e m a r f f o t u o d e l b a n e s i c i g o l n o i t c e t e d n r e t t a p g n i m a r f e h t . 8 3 0 3 s e h t n i c i g o l e m a r f l i t n u d e l b a n e s n i a m e r d n a , f o o n o e g d e g n i s i r a y b . r e g n o l s i r e v e h c i h w , w o l t e s s i f o o n e h w r o d e t c e t e d s i y r a d n u o b f o h t d i w e s l u p m u m i n i m a h t i w l a n g i s s u o n o r h c n y s a n a s i f o o t e s e r r e t f a d e r i u q e r s i f o o n o e g d e g n i s i r . d o i r e p k l c o p e n o . p i h c e h t e z i l a i t i n i o t a l t t d s b l t t d s c l t t d s d l t t d s l t t v li5 1 u 6 1 r 7 1 n 6 1 j s i l t t d s n e h w . ) 1 c i g o l ( h g i h e v i t c a . t c e t e d l a n g i s l t t v l o t d e c r o f y l l a n r e t n i e b l l i w s n i p n / p d s r e h t n o a t a d e h t , e v i t c a n i s n i p n / p d s r e h t n o a t a d , e v i t c a s i l t t d s n e h w . o r e z t n a t s n o c a . y l l a m r o n d e s s e c o r p e b l l i w
17 S3038 sonet/sdh/atm oc-12 quad transceiver may 31, 2001 / revision c table 10. power and ground pin assignments e m a n n i ps e s a i l a . o n s l a n g i s # n i pn o i t p i r c s e d d d v ax a d d v5 8 c 6 a 1 a 6 1 a 3 1 a . e s i o n w o l ) d d v ( r e w o p g o l a n a s s v ax a s s v5 8 b 7 b 4 c 5 1 b 1 1 d . ) s s v ( d n u o r g g o l a n a d d vx d d v5 9 d 6 b 4 b 5 1 a 2 1 a . ) d d v ( y r t i u c r i c d e e p s h g i h r o f r e w o p s s vx s s v x b u s s s v 0 16 d 4 a 2 a 8 d 7 a 0 1 b 1 1 a 4 1 a 3 1 c 4 1 b . ) s s v ( y r t i u c r i c d e e p s h g i h r o f d n u o r g d d v pr w p l c e p45 1 e 5 1 d 6 1 g 6 1 e . ) d d v ( r e w o p l c e p s s v pd n g l c e p16 1 c. ) s s v ( d n u o r g l c e p d d v dr w p g i d 1 r w p g i d 92 c 2 b 1 b 2 1 d 3 d 7 1 j 4 l 3 e 9 p . ) d d v ( r e w o p y r t i u c r i c e r o c s s v dd n g g i d 1 d n g g i d s d n g g i d 0 11 c 6 1 b 3 r 3 c 2 d 5 1 j 4 n 4 f 0 1 p 6 1 h . ) s s v ( d n u o r g y r t i u c r i c e r o c d d v tr w p l t t84 g 3 n 1 e 5 p 4 k 4 h 8 p 7 p . ) d d v ( o / i l t t r o f r e w o p s s v td n g l t t0 13 f 2 e 1 d 4 m 4 j 3 l 6 p 4 r 4 p 8 r . ) s s v ( o / i l t t r o f d n u o r g d n g / r w p l a t o t 7 6 c n83 k 3 g 1 g 2 t 3 p 2 p 7 t 6 t . d e t c e n n o c t o n 1 p a c 2 p a c 23 1 d 4 1 c . s r o t s i s e r d n a r o t i c a p a c r e t l i f p o o l l a n r e t x e r o f s n i p . 0 2 e r u g i f e e s e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d b e l dl t ti 4 1 ds i e c r u o s t u p n i , w o l n e h w . e l b a n e k c a b p o o l c i t s o n g a i d e h t , h g i h n e h w . l e n n a h c h c a e r o f l e s d s r e h t y b d e n i m r e t e d . t u p n i s t i o t k c a b d e p o o l s i l e n n a h c h c a e r o f t u p t u o l a i r e s . h g i h = b e l d n e h w d e h c l e u q s e r a n / p x 1 d s t d n a n / p x 0 d s t table 9. receiver control signals pin assignment and descriptions
18 S3038 sonet/sdh/atm oc-12 quad transceiver may 31, 2001 / revision c figure 10. quad transceiver pinout-bottom view a b c d e f g h j k l m n p r t u 1 d d v ad d v ds s v ds s v td d v t6 a t u o pc n3 a t u o p0 a t u o pn a k l c o pb p f7 b t u o p5 b t u o p1 b t u o p0 b t u o pn b k l c o pp b k l c o p 2 s s vd d v dd d v ds s v ds s v ta p f7 a t u o p4 a t u o p2 a t u o pp a k l c o p6 b t u o p4 b t u o p3 b t u o pc nc p fc n6 c t u o p 3 l e s a d s rn 1 a d s rs s v dd d v dd d v ds s v tc n5 a t u o p1 a t u o pc ns s v t2 b t u o pd d v tc ns s v d7 c t u o p3 c t u o p 4 s s vd d vs s v ap 1 a d s rk c o l _ h cs s v dd d v td d v ts s v td d v td d v ds s v ts s v ds s v ts s v t4 c t u o pn c k l c o p 5 l e s b d s rn 0 b d s rn 0 a d s rp 0 a d s r d d v t5 c t u o p2 c t u o pp c k l c o p 6 d d v ad d vp 0 b d s rs s v s s v t1 c t u o pc nd p f 7 s s vs s v ap 1 b d s rn 1 b d s r d d v t0 c t u o pc n6 d t u o p 8 p 1 c d s rs s v ad d v as s v d d v ts s v t7 d t u o p5 d t u o p 9 n 1 c d s rn 0 c d s rl e s c d s rd d v d d v d3 d t u o p4 d t u o p2 d t u o p 0 1 p 0 c d s rs s vp 0 d d s rn 0 d d s r s s v d1 d t u o pp d k l c o pn d k l c o p 1 1 s s vl e s d d s rp 1 d d s rs s v a 5 a n i p6 a n i p7 a n i p0 d t u o p 2 1 d d vn 1 d d s rl e s k l cd d v d 0 a n i p1 a n i p3 a n i pa k l c i p 3 1 d d v ae d o m ts s v1 p a c 6 b n i pb k l c i p2 a n i p4 a n i p 4 1 s s vs s v2 p a cb e l dp 1 a d s tp 1 b d s tn 1 c d s tp 1 d d s tk l c p3 d n i pd k l c i p2 c n i p7 c n i p1 b n i p3 b n i p7 b n i pa f o o 5 1 d d vs s v at e s e rd d v pd d v pn 1 b d s tp 1 c d s tn 1 d d s ts s v d2 d n i p7 d n i p0 c n i p5 c n i pc k l c i p0 b n i p2 b n i pa l t t d s 6 1 d d v as s v ds s v pn 1 a d s td d v pp 0 c d s td d v ps s v dd l t t d s1 d n i p5 d n i p6 d n i p1 c n i p4 c n i pb l t t d sb f o o5 b n i p 7 1 p 0 a d s tn 0 a d s tp 0 b d s tn 0 b d s tn 0 c d s tp 0 d d s tn 0 d d s tk l c f e rd d v dd f o o0 d n i p4 d n i pc l t t d sc f o o3 c n i p6 c n i p4 b n i p S3038 208 tbga bottom view
19 S3038 sonet/sdh/atm oc-12 quad transceiver may 31, 2001 / revision c figure 11. 208 tbga package r e w o p e g a k c a p x a m q ) r i a l l i t s ( a j q c j w 4 . 3w / c 7 . 7 1w / c 0 . 3 thermal management
20 S3038 sonet/sdh/atm oc-12 quad transceiver may 31, 2001 / revision c table 11. performance specifications * noise on refclk should be less than 14 ps rms in a jitter frequency band from 12 khz to 5 mhz. r e t e m a r a pn i mp y tx a ms t i n un o i t i d n o c o c v l a n i m o n y c n e u q e r f r e t n e c 8 0 . 2 2 6z h m r e t t i j t u p t u o a t a d 2 1 - s t s . k l c . f e r z h m 8 8 . 8 3 C . k l c f e r z h m 6 7 . 7 7 C 1 0 . 0 5 7 0 0 . 0 ) s m r ( i uk c o l n i , r e t t i j s m r k c o l c e c n e r e f e r * e c n a r e l o t y c n e u q e r f 0 2 -0 2 +m p p t u p t u o t e n o s t e e m o t d e r i u q e r n o i t a c i f i c e p s y c n e u q e r f 2 1 - s t s / 2 1 - c o e g n a r e r u t p a c e g n a r k c o l 0 0 2 % 2 1 m p pe c n e r e f e r d e x i f o t t c e p s e r h t i w y c n e u q e r f e m i t k c o l n o i t i s i u q c a 6 1c e s % 0 2 f o y t i s n e d n o i t i s n a r t m u m i n i m p u d e r e w o p y d a e r l a e c i v e d h t i w . k l c . f e r d i l a v d n a k c o l c e c n e r e f e r e l c y c y t u d t u p n i 0 30 7% & e s i r k c o l c e c n e r e f e r s e m i t l l a f 0 . 2s ne d u t i l p m a f o % 0 8 o t % 0 2 t a e c n e r e f f i d y c n e u q e r f f o t u o s e o g l l p e h t h c i h w o t d e r a p m o c k l c f e r ( k c o l o c v n w o d d e d i v i d e h t ) k c o l c 0 5 20 9 20 3 3m p p t a e c n e r e f f i d y c n e u q e r f s e o g l l p e v i e c e r e h t h c i h w k l c f e r ( k c o l o t n i d e d i v i d e h t o t d e r a p m o c ) k c o l c o c v n w o d 0 5 20 9 20 3 3m p p f o h t g n e l n u r m u m i x a m t u o e r o f e b t u p n i a t a d l a i r e s d e r a l c e d s i k c o l f o 0 80 0 0 1i u. n / p d s r n o s n o i t i s n a r t o n r e t t i j 2 1 - s t s / 2 1 - c o e c n a r e l o t 4 . 0i u . r e t t i j t u p n i l a d i o s u n i s a t a d p / i t a d r e s n o e d u t i l p m a . z h m 5 o t z h k 2 1 m o r f s t u p n i
21 S3038 sonet/sdh/atm oc-12 quad transceiver may 31, 2001 / revision c table 13. recommended operating conditions table 12. absolute maximum ratings r e t e m a r a pn i mp y tx a ms t i n u e r u t a r e p m e t e g a r o t s5 6 -0 5 1c d n g o t t c e p s e r h t i w d d v n o e g a t l o v5 . 0 -0 . 7 +v n i p t u p n i l t t y n a n o e g a t l o v5 . 0 -7 4 . 3v n i p t u p n i l c e p v l y n a n o e g a t l o v0d d vv t n e r r u c k n i s t u p t u o l t t8a m t n e r r u c e c r u o s t u p t u o l t t8a m t n e r r u c e c r u o s t u p t u o l c e p v l d e e p s h g i h0 5a m y t i v i t i s n e s d s e 1 0 0 5 1v r e t e m a r a pn i mp y tx a ms t i n u s a i b r e d n u e r u t a r e p m e t t n e i b m a00 7c s a i b r e d n u e r u t a r e p m e t n o i t c n u j0 3 1c , d d v o i l c e , d d v l c e , d d v l t t n o e g a t l o v s s v / d n g o t t c e p s e r h t i w d d v a d n a 5 3 1 . 33 . 35 6 4 . 3v n i p t u p n i l t t y n a n o e g a t l o v05 6 4 . 3v n i p t u p n i l c e p v l y n a n o e g a t l o v d d v v 2 - d d vv n i p a t a d l t t n o e g a t l o v05 6 4 . 3v s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us t n e m m o c t fe c n a r e l o t y c n e u q e r f0 0 1 -0 0 1 +m p p d t 2 - 1 y r t e m m y s0 40 6% . t p % 0 5 t a e l c y c y t u d t r c r t , f c r e m i t l l a f d n a e s i r k l c f e r2s n. % 0 8 - % 0 2 table 14. reference clock requirements 1. human body model.
22 S3038 sonet/sdh/atm oc-12 quad transceiver may 31, 2001 / revision c table 16. transmit signals characteristics table 15. ttl input/output dc characteristics s r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us t n e m m o c v h o ) l t t ( e g a t l o v h g i h t u p t u o4 . 28 . 2d d vv i n i m = d d v h o a m 4 - = v l o ) l t t ( e g a t l o v w o l t u p t u od n g5 2 0 .5 . 0v i n i m = d d v l o a m 4 = v h i ) l t t ( e g a t l o v h g i h t u p n i0 . 2v v l i ) l t t ( e g a t l o v w o l t u p n id n g8 . 0v i h i ) l t t ( t n e r r u c h g i h t u p n i0 4a v n i x a m = d d v , v 4 . 2 = i l i ) l t t ( t n e r r u c w o l t u p n i0 0 6a v n i x a m = d d v , v 4 . 2 = i c c t n e r r u c y l p p u s5 2 80 8 9a m. n r e t t a p 0 1 0 1 p d n o i t a p i s s i d r e w o p7 . 24 . 3w . n r e t t a p 0 1 0 1 v f f i d g n i w s e g a t l o v t u p n i l a i t n e r e f f i d . n i m s t u p n i l c e p v l l a i t n e r e f f i d r o f 0 5 10 0 3 1v m. 2 1 e r u g i f e e s d v t u o g n i w s e g a t l o v t u p t u o l a i r e s ) d e d n e - e l g n i s ( 0 0 60 0 6 1v m0 5 w v 0 . 2 - d d v o t c n i e c n a t i c a p a c t u p n i3f p s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us t n e m m o c r e t t i j l a t o t) p - p ( r e t t i j t u p t u o a t a d l a i r e s2 9 1s p a n o d e t s e t , k a e p - o t - k a e p h t i w d e r u s a e m . s i s a b e l p m a s 2 a 7 . n r e t t a p 1 - t r d s t , f d s e m i t l l a f d n a e s i r a t a d l a i r e s0 5 3s p a n o d e t s e t % 0 8 o t % 0 2 h t i w d e r u s a e m . s i s a b e l p m a s . d a o l f p 0 1 table 17. receive signal characteristics s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us t n e m m o c t u p n i y t i v i t i s n e s y l b a i l e r o t t u p n i n o d e r i u q e r g n i w s a t a d r e v o c e r 0 0 1v m t r d s t , f d s e m i t l l a f d n a e s i r a t a d l a i r e s0 0 5s p a n o d e t s e t % 0 8 o t % 0 2 . s i s a b e l p m a s
23 S3038 sonet/sdh/atm oc-12 quad transceiver may 31, 2001 / revision c v(+) v(? v(+) ?v(? v swing v d = 2 x v swing figure 12. differential voltage note: v(+) C v(-) is the algebraic difference of the input signals.
24 S3038 sonet/sdh/atm oc-12 quad transceiver may 31, 2001 / revision c l o b m y sn o i t p i r c s e dn i mx a ms t i n us t n e m m o c e l c y c y t u d k l c o p0 40 6% e m i t l l a f / e s i r k l c o p3s n s t t u o p k l c o p . t . r . w p u t e s a t a d3s n h t t u o p k l c o p . t . r . w e m i t d l o h a t a d3s n p t t u o p d i l a v ] 0 : 7 [ x t u o p o t w o l k l c o p2 -2s n table 18. receiver timing (see figure 13) 1. all ac measurements are made from the reference level of the clock 1.4v to the valid input or output data level (0.8 or 2v). table 19. pclk timing l o b m y sn o i t p i r c s e dn i mx a ms t i n us t n e m m o c d t k l c p k l c p o t k l c f e r m o r f y a l e d25 . 7s n0 = l e s k l c d t k l c p k l c p o t k l c f e r m o r f y a l e d25 . 7s n1 = l e s k l c figure 13. receiver output timing diagram notes on output timing: 1. output propagation delay time of lvttl outputs is the time in nanoseconds from the 1.4v point of the reference signal to the valid input or output data level (0.8v or 2v). 2. maximum output propagation delays of lvttl outputs are measured with a 10 pf load on the outputs. 3. output propagation delay time of high speed lvpecl outputs is the time in nano seconds from the cross-over point of the reference signal to the cross-over point of the output. pout[7:0] poclk ts pout th pout duty cycle min duty cycle max tp pout 2v 0.8v 1.4v figure 14. pclk timing (see table 19) td pclk refclk pclk
25 S3038 sonet/sdh/atm oc-12 quad transceiver may 31, 2001 / revision c figure 15. transmitter timing (normal or channel lock mode, tmode = 0) table 20. S3038 transmitter timing (normal or channel lock mode, tmode = 0) figure 16. transmitter timing (normal or channel lock mode tmode = 1) table 21. S3038 transmitter timing (normal or channel lock mode, tmode = 1) refclk pinx[7:0] t s t h serial data out piclkx, piclka pinx[7:0] t s t h serial data out s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us n o i t i d n o c t s k l c f e r . t . r . w p u t e s a t a d5 . 0-s n. 1 e t o n e e s t h k l c f e r . t . r . w d l o h a t a d5 . 1-s n s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us n o i t i d n o c t s k l c i p . t . r . w p u t e s a t a d1-s n. 1 e t o n e e s t h k l c i p . t . r . w d l o h a t a d5 . 0-s n 1. all ac measurements are made from the reference voltage level of the clock (1.4v) to the valid input or output data levels (0.8v or 2.0v). 1. all ac measurements are made from the reference voltage level of the clock (1.4v) to the valid input or output data levels (0.8v or 2.0v).
26 S3038 sonet/sdh/atm oc-12 quad transceiver may 31, 2001 / revision c table 22. power and ground application information n o i t c n u f n o s e m a n t u o n i p r e t s a m e m a n n i ps n o i t c u r t s n i g o l a n a a d d vd d v a e d i v o r p . y l p p u s v 3 . 3 d e r e t l i f r o e s i o n w o l o t t c e n n o c ) f p 0 0 1 , f 1 . 0 ( l a u d e s u . s s v - a o t g n i s s a p y b f h l a c o l . g n i s s a p y b a s s vs s v a. e n a l p d n u o r g o t t c e n n o c d e e p s h g i h d d vd d v l a c o l e d i v o r p . v 3 . 3 o t n o i t c e n n o c e c n a d e p m i w o l ) f p 0 0 1 , f 1 . 0 ( l a u d e s u . e n a l p d n g o t g n i s s a p y b . g n i s s a p y b b u s s s v s s vs s v. e n a l p d n u o r g o t t c e n n o c o / i l c e p r w p l c e pd d v p e d i v o r p . v 3 . 3 o t n o i t c e n n o c e c n a d e p m i w o l e d i v o r p ) f p 0 0 1 , f 1 . 0 ( l a u d e s u . e n a l p d n g o t g n i s s a p y b l a c o l . g n i s s a p y b d n g l c e ps s v p. e n a l p d n u o r g o t t c e n n o c e r o c r w p g i dd d v d e d i v o r p . v 3 . 3 o t n o i t c e n n o c e c n a d e p m i w o l e d i v o r p . s r o t i c a p a c f 1 . 0 g n i s u g n i s s a p y b l a c o l d n g g i ds s v d. e n a l p d n u o r g o t t c e n n o c o / i l t t r w p l t td d v t g n i s s a p y b l a c o l e d i v o r p . e n a l p r e w o p v 3 . 3 o t t c e n n o c . s r o t i c a p a c f 1 . 0 g n i s u d n g l t ts s v t. e n a l p d n u o r g o t t c e n n o c l e v e l c i g o l a nr w p. y r a s s a c e n g n i s s a p y b o n . d d v o t n o i t c e n n o c c i g o l a nd n g. s s v o t n o i t c e n n o c c i g o l
27 S3038 sonet/sdh/atm oc-12 quad transceiver may 31, 2001 / revision c receiver framing figure 17 shows a typical reframe sequence in which a byte realignment is made. the frame and byte boundary detection is enabled by the rising edge of oof and remains enabled while oof is high. both boundaries are recognized upon receipt of the third a2 byte which is the first data byte to be reported with the correct byte alignment on the out- going data bus (poutx[7:0]). concurrently, the frame pulse is set high for one poclk cycle. when interfacing with a section terminating device, the oof input remains high for one full frame after the first frame pulse while the section terminating device verifies internally that the frame and byte alignment are correct, as shown in figure 17. since at least one framing pattern has been detected since the rising edge of oof, boundary detection is dis- abled when oof is set low. the frame and byte boundary detection block is acti- vated by the rising edge of oof, and stays active until the first fp pulse or until oof goes low, which- ever occurs last. figure 18 shows a typical oof timing pattern which occurs when the S3038 is con- nected to a down stream section terminating device. oof remains high for one full frame after the first fp pulse. the frame and byte boundary detection block is active until oof goes low. figure 19 shows the frame and byte boundary detec- tion activation by a rising edge of oof, and deactivated by the first fp pulse. figure 17. frame and byte detection note 1: range of input to output delay can be 1.5 to 2.5 poclk cycles. figure 18. oof operation timing with pm5312 sttx or pm5355 suni-622 boundary detection enabled oof fp oof fp boundary detection enabled figure 19. alternate oof timing a1 a1 a1 a2 a2 a2 a2 a2 note 1 a1 a1 a1 a2 a2 a2 (28h) invalid data valid data recovered clock/ refclk oof rsd poutx[7:0] poclk fp
28 S3038 sonet/sdh/atm oc-12 quad transceiver may 31, 2001 / revision c figure 20. external loop filter 270 22 nf 270 cap1 cap2 figure 22. high speed differential inputs figure 21. serial output load 1.5k 1.5k 0.01 f 0.01 f 100 0.01 f 0.01 f vcc - 1.3 v
29 S3038 sonet/sdh/atm oc-12 quad transceiver may 31, 2001 / revision c x xxxx xx prefix device package ordering information x i f e r pe c i v e de g a k c a p t i u c r i c d e t a r g e t n i C s8 3 0 3a g b t 8 0 2 C b t amcc is a registered trademark of applied micro circuits corporation. copyright ? 2001 applied micro circuits corporation d485/r709 amcc reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the informati on being relied on is current. amcc does not assume any liability arising out of the application or use of any product or circuit described herein, neither do es it convey any license under its patent rights nor the rights of others. amcc reserves the right to ship devices of higher grade in place of those of lower grade. amcc semiconductor products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. applied micro circuits corporation 6290 sequence drive, san diego, ca 92121 phone: (858) 450-9333 ? (800) 755-2622 ? fax: (858) 450-9885 http://www.amcc.com c e r t i f i e d i s o 9 0 0 1

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